Some types of field effect transistors (FETs) have three-dimensional, non-planar configurations including fin-like structures. Such field effect transistors are referred to as FinFETs. Substrates employed for forming FinFETs may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other electrically insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed immediately following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor, removing the dummy gate, and replacing the removed dummy gate with actual gate materials. Doped semiconductor material such as silicon germanium (SiGe) may be provided by selective epitaxial growth on the sidewalls of the fin structure(s) during fabrication of FinFETs. Such growth results in faceted structures that, in some cases, merge into a continuous volume and in other cases remain isolated. Doped silicon or silicon germanium grown epitaxially on the fins increases the volumes of the source/drain regions. Such epitaxial growth proceeds from the fins to self-limited, diamond-shaped volumes.
Device pitch scaling at each CMOS technology node continues to reduce the metal contact area to the source/drain junctions of CMOS devices, including FinFET devices. Metal contact length is limited to less than twenty nanometers in some devices, resulting in high access resistance and therefore reduced performance. The problem is further exacerbated in FinFET devices where the current path includes the entire spacer region and the entire fin height before it reaches the metal contact.